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complete 10-bit 18 msps a ccd signal processor features 18 msps correlated double sampler (cds) 6 db to 40 db 10-bit variable gain amplifier (vga) low noise clamp circuits preblanking function 10-bit 18 msps a/d converter 3-wire serial digital interface 3 v single supply operation low power cmos 48-lead lqfp package applications pc cameras digital still cameras product description t he ad9804 is a complete analog signal processor for ccd applications. it features an 18 mhz single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan area ccd arrays. the ad9804s signal chain consists of an input clamp, correlated double sampler (cds), digitally controlled vga, black level clamp, and a 10-bit a/d converter. the internal vga gain register is programmed through a 3-wire serial digital interface. rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. ad9804
functional block diagram pblk avdd avss clpob 6db to 40db 10 sdata sck sl vga vga gain register bandgap reference internal timing internal bias 10 clp 10-bit adc digital ad9804 interface cds clp drvdd drvss dout ccdin vr t vrb clpdm cml dvdd dvss shp shd dataclk one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000
ad9804Cspecifications analog specifications (t min to t max , avdd = dvdd = 3.0 v, f dataclk = f shp = f shd = 18 mhz, unless otherwise noted.) parameter min typ max unit temperature range operating storage C20 C65 +85 +150 c c power supply voltage analog, digital, digital driver 2.8 3.0 3.6 v power consumption 85 mw maximum clock rate 18 mhz correlated double sampler (cds) allowable ccd reset transient 1 max input range before saturation 1 max ccd black pixel amplitude 1 500 1.0 100 mv v p-p mv variable gain amplifier (vga) gain control resolution gain range (vga gain curve shown in figure 5) min gain (code 95) max gain (code 1023) 4 38 1024 6 40 8 42 steps d b db black level clamp clamp level (at adc output) 32 lsb a/d converter resolution no missing codes full-scale input voltage 10 10 2.0 bits bits guaranteed v voltage reference reference top voltage (vrt) reference bottom voltage (vrb) 2.0 1.0 v v notes
1 input signal characteristics defined as follows:
1v max input signal range 100mv max optical black pixel 500mv typ reset transient specifications subject to change without notice. digital specifications (drvdd = 2.7 v, c l = 20 pf.) parameter symbol min typ max unit logic inputs high level input voltage v ih 2.1 v low level input voltage v il 0.6 v high level input current i ih 10 a low level input current i il 10 a input capacitance c in 10 pf logic outputs high level output voltage v oh 2.1 v low level output voltage v ol 0.6 v high level output current i oh 50 a low level output current i ol 50 a specifications subject to change without notice. C2C rev. 0
ad9804 timing specifications (c l = 20 pf, f clk = 18 mhz, timing shown in figures 1 and 2.) parameter symbol min typ max unit sample clocks dataclk, shp, shd clock period t conv 55.6 ns dataclk hi/low pulsewidth t adc 20 27.7 ns shp pulsewidth t shp 10 14 ns shd pulsewidth t shd 10 14 ns clpdm pulsewidth t cdm 4 1 0 p i xels clpob pulsewidth 1 t cob 2 1 0 p i xels shp rising edge to shd falling edge t s1 20 27 ns shp rising edge to shd rising edge t s2 20 27 ns internal clock delay t id 3.0 ns inhibited clock period t inh 10 ns data outputs output delay t od 14.5 16 ns output hold time t h 6.0 7.6 ns pipeline delay 9 cycles serial interface maximum sck frequency f sclk 10 mhz sl to sck setup time t ls 10 ns sck to sl hold time t lh 10 ns sdata valid to sck rising edge setup t ds 10 ns sck falling edge to sdata valid hold t dh 10 ns sck falling edge to sdata valid read t dv 10 ns notes
1 minimum clpob pulsewidth is for functional operation only. wider typical pulses are recommended to achieve low noise clamp perf ormance.
specifications subject to change without notice
ordering guide absolute maximum ratings parameter with respect to min max unit avdd avss C0.3 +3.9 v dvdd dvss C0.3 +3.9 v drvdd drvss C0.3 +3.9 v digital outputs drvss C0.3 drvdd + 0.3 v shp, shd, dataclk dvss C0.3 dvdd + 0.3 v clpob, clpdm, pblk dvss C0.3 dvdd + 0.3 v sck, sl, sdata dvss C0.3 dvdd + 0.3 v vrt, vrb, cmlevel avss C0.3 avdd + 0.3 v byp1C4, ccdin avss C0.3 avdd + 0.3 v junction temperature 150 c lead temperature 300 c (10 sec) temperature package package model range description option ad9804jst C20 c to +85 c t hin plastic st-48 quad flatpack (lqfp) thermal characteristics thermal resistance 48-lead lqfp package ja = 92 c/w caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9804 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device rev. 0 C3C
ad9804 pin configuration nc nc (lsb) d0 d1 d2 d3 d4 d5 d6 d7 d8 (msb) d9 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 43 42 41 40 37 pin 1 identifier top view (not to scale) 36 35 34 33 32 31 30 29 28 27 26 25 ad9804 sck sdata sl nc dvss rstb dvss dvss dvdd vrb vrt cml drvdd drvss dvss dataclk dvdd nc pblk clpob shp shd clpdm nc nc avss nc avdd byp4 nc ccdin byp2 byp1 avdd avss avss nc = no connect pin function descriptions pin no. mnemonic type description 1, 2, 18, 24, 31 nc nc internally not connected 34, 36, 45 3C12 d0Cd9 do digital data outputs 13 drvdd p digital output driver supply 14 drvss p digital output driver ground 15, 41, 42, 44 dvss p digital ground 16 dataclk di digital data output latch clock 17, 40 dvdd p digital supply 19 pblk di preblanking clock input 20 clpob di black level clamp clock input 21 shp di cds sampling clock for ccds reference level 22 shd di cds sampling clock for ccds data level 23 clpdm di input clamp clock input 25, 26, 35 avss p analog ground 27, 33 avdd p analog supply 28 byp1 ao internal bias level decoupling 29 byp2 ao internal bias level decoupling 30 ccdin ai analog input for ccd signal 32 byp4 ao internal bias level decoupling 37 cml ao internal bias level decoupling 38 vrt ao a/d converter top reference voltage decoupling 39 vrb ao a/d converter bottom reference voltage decoupling 43 rstb di chip reset control. active low 46 sl di serial digital interface load pulse. 47 sdata di serial digital interface data 48 sck di serial digital interface clock type: ai = analog input, ao = analog output, di = digital input, do = digital output, p = power. C4C rev. 0
ad9804
timing diagrams ccd signal shp shd dataclk output data nC10 nC9 nC8 nC1 n n n+1 n+2 n+9 n+10 t id t id t s1 t s2 t cp t inh t od t h notes: 1. recommended placement for dataclk rising edge is between the shd rising edge and next shp falling edge. 2. ccd signal is sampled at shp and shd rising edges. figure 1. pixel rate timing horizontal blanking effective pixels optical black pixels dummy pixels effective pixels ccd signal clpob clpdm pblk output ob pixel data dummy black effective data effective pixel data data notes: 1. clpob and clpdm will overwrite pblk. pblk will not affect clamp operation if overlapping clpdm and/or clpob. 2. pblk signal is optional. 3. digital output data will be all zeros during pblk. output data latency is 9 dataclk cycles. figure 2. typical line clamp timing rev. 0 C5C
ad9804 programming the serial interface table i. vga gain register contents (default value x096) msb d9 d8 d7 d6 d5 d4 d3 d2 d1 lsb d0 gain (db) 0 0 0 1 0 1 ? 1 1 1 1 6.0 ? ? ? 1 1 1 1 1 ? 1 1 1 1 0 ? 39.965 1 1 1 1 1 1 1 1 1 1 40.0 rnw address bits data bits sdata sck sl 0 0 0 1 0 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 t ds t dh t ls t lh notes: 1. sdata bits are internally latched on the rising edges of sck. 2. rnw = read, not write. set low for write operation. 3. internal vga gain register update occurs at sl rising edge. figure 3. serial write operation rnw address bits data bits sdata 1 d 0 d 1 d2 d3 d4 d5 d6 d7 d8 d9 d10 t ds t dh t ls t lh notes: 1. rnw = read, not write. set high for read operation. 2. the rnw bit and the four address bits must be written to the ad9804. sdata is latched on sck rising edges. 3. serial data from vga gain register is valid starting after the 5th sck falling edge , and is updated on sck falling edges. t dv 0 0 1 0 sck sl figure 4. serial readback operation C6C rev. 0
ad9804
variable gain amplifier (vga) operation details t he vga stage provides a gain range of 6 db to 40 db, pro- gra mmable with 10-bit resolution through the serial digital interface. the minimum gain of 6 db is needed to match a 1 v input signal with the adc full-scale range of 2 v. when com- pared to 1 v full-scale systems (such as adis ad9803), the equivalent gain range is 0 db to 34 db. the vga gain curve is divided into two separate regions. when t he vga gain register code is between 0 and 511, the curve follows a (1 + x)/(1 C x) shape, which is similar to a linear-in- db characteristic. from code 512 to code 1023, the curve follows a linear-in-db shape. the exact vga gain can be calculated f or any gain register value by using the following two equations: code range gain equation (db) 0C511 gain = 20 log 10 ([658 + code ]/[658 C code ]) + 3.6 512C1023 gain = (0.0354)( code ) + 3.6 as shown in the analog specifications, only the vga gain range from 2 db to 36 db has been specified. this corresponds to a vga gain code range of 95 to 1023. 40 34 28 22 16 10 4 0 127 255 383 511 639 767 895 1023 vga gain register code figure 5. vga gain curve applications information the ad9804 is a complete analog front-end (afe) product for pc camera, digital still camera, and camcorder applications. as shown in figure 6, the ccd image (pixel) data is buffered and sent to the ad9804 analog input through a series input vga gain C db capacitor. the ad9804 performs the dc restoration, cds, gain ad justment, black level correction, and analog-to-digital con- v ersion. the ad9804s digital output data is then processed by the image pr ocessing asic. the internal registers of the ad9804 used to c ontrol gain, offset level, and other functions are pro- grammed by the asic or microprocessor through a 3-wire serial digital interface. a system timing generator provides the clock signals for both the ccd and the afe. generating the reset (rstb) signal after power-on, the ad9804 must be reset using pin 43 (rstb). the reset pulse must be an active low signal, which goes low for at least 100 ns after the power supplies have settled. after the rstb signal returns high, the ad9804 is internally reset to the default vga gain register value. if a system reset pulse is not available, a simple rc network may be used, as shown in figure 7. the time constant of this network should be comparable to th e power-on time of the ad9804s power supplies. for example, if the power supplies have a power-on time of 10 ms, the rc network should have a time constant of 10 ms, giving r = 10 k ? and c = 1.0 f. serial writes to the ad9804 internal registers must not be per- f ormed until 20 s after the reset pulse has occurred. this allows en ough time for internal calibration routines to be completed. sdata and sck may be active before the reset sequence, but sl should be held logic high until 20 s or more after the reset. alternatively, placing series resistors close to the digital out- put pins may help reduce noise. grounding and decoupling recommendations as shown in figure 7, a single ground plane is recommended for the ad9804. this ground plane should be as continuous as possible, particularly around pins 25 through 39. this will ensure that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and their respective ground pins. all decoupling capacitors should be located as close as possible to the package pins. a single clean power supply is recommended for the ad9804, but a separate d igital driver supply may be used for drvdd (pin 13). drvdd should always be decoupled to drvss (pin 14), which should be connected to the analog ground plane. advantages of using a s eparate digital driver supply include using a lower voltage (2.7 v) to match levels with a 2.7 v asic, reducing digital power dissipa- tion, and r educing potential noise coupling. if the digital outputs ( pins 3C12) must drive a load larger than 20 pf, buffering is recommended to reduce digital code transition noise. ccd ccdin buffer v out 0.1?f adc out vga gain serial interface digital outputs digital image processing asic timing generator v-drive ccd timing cds/clamp timing ad9804 figure 6. system block diagram rev. 0 C7C
c01633C0C10/00 (rev. 0) printed in u.s.a. ad9804 3v analog supply ccd signal analog 0.1?f supply data outputs drvdd drvss dvss dataclk dvdd nc pblk clpob shp shd clpdm nc 13 14 15 16 17 18 19 20 21 22 23 24 1 12 37 48 47 46 45 44 39 38 43 42 41 40 pin 1 identifier top view (not to scale) ad9804 36 25 nc nc nc (lsb) d0 d1 d2 d3 d4 d5 d6 d7 d8 (msb) d9 sck sdata sl nc dvss rstb dvss dvss dvdd vrb vrt cml analog supply 10 3 serial interface 0.1?f 1.0?f 1.0?f 0.1?f 1.0?f 10k? 6 0.1?f 0.1?f 3v analog supply 3v driver supply nc = no connect clock inputs figure 7. ad9804 circuit configuration 2 3 4 5 6 7 8 9 10 11 35 nc avdd byp4 nc ccdin avss 0.1?f 0.1?f 0.1?f 3v 34 33 32 31 30 byp2 byp1 avdd avss avss 0.1?f 0.1?f 3v 29 28 27 26 outline dimensions dimensions shown in inches and (mm). 48-lead, lqfp (st-48) 0.063 (1.60) top view (pins down) 1 12 13 25 24 36 37 48 0.019 (0.5) bsc 0.276 (7.00) bsc sq 0.011 (0.27) 0.006 (0.17) 0.354 (9.00) bsc sq max 0.030 (0.75) 0.018 (0.45) 0.008 (0.2) 0.004 (0.09) 0? min coplanarity 0.003 (0.08) 7 ? 0 ? 0.057 (1.45) 0.053 (1.35) 0.006 (0.15) seating 0.002 (0.05) plane C8C rev. 0

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